Various circuits and techniques are used to achieve lock in phase lock loop circuitry. For example, FIGS. 1-3 depicts existing circuitry and background in this regard, with FIG. 1A depicting an existing phase frequency detector and FIG. 3 depicting an existing phase lock loop (PLL) circuit. In the PLL configuration shown in FIG. 3, the phase frequency detector (PFD) 310 pulls in the frequency and locks in the phase. However, for a wide-range frequency synthesizer, various PLL acquisition techniques such as here in FIGS. 1-3 can be unsatisfactory. Among other things, such techniques can be too slow if the preset frequency and target frequency are quite different. Negative gain and cycle slipping issues can also arise. When a phase frequency detector (PFD) reaches its limit, for example, one of the clock edges is ignored. This can lead to cycle slipping, which should occur when a second clock edge catches up before the previous clock edge comparison finishes. Further, cycle slipping can occur too early in prior circuitry. For example, cycle slipping may occur as soon as the second clock edge is blocked by the rear edge of the “up”, “down” signals, which can happen too early and even generate a negative gain.
In addition, existing approaches to frequency detection, such as rotational frequency detectors and quadricorrelators, often have limited detection ranges and/or also have a variety of other drawbacks. Rotational frequency detection, for example, typical requires numerous clocks/signals such as internal quadrature clocks (90 degree offset clocks), an I clock (l-clk 902), and a Q clock (Q-clk 904) as well as latching and comparison of the various states thereof. Further, other approaches such as quadricorrelators also involve quadrature clocks, may operate as a function of DC components, and are also an analog solution, thus present associated challenges to adapt to digital circuitry.
Overall, there is a need for systems and methods that may, inter alia, possess improved frequency difference detection, involve fewer clock signals, be digital solutions, more quickly adjust the frequency of a feedback clock, and/or otherwise achieve lock-in condition more quickly with respect to various circuitry.